|  | # TKGate 2.1: Digital Circuit Editor and Simulator © 1987-2015 by Jeffery P. Hansen © 2015-2018 by Andrey V. Skvortsov This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.

TkGate is a graphical editor and event-driven simulator for digital circuits with a tcl/tk-based interface. Supported circuit elements include basic gates (AND, OR, etc.), tri-state gates, adders, multipliers, registers, memories and mos transistors. Hierarchical design is also supported with support for user defined modules. Save files are based on the Verilog netlist format.

## Contents:

1. Introduction to TkGate
   - 1.1 Command Line Options
   - 1.2 History of TkGate
2. Using the Editor
   - 2.1 Understanding the TKGate Interface
   - 2.2 Loading and Saving Circuits
   - 2.3 Loading Libraries
   - 2.4 Basic Editing Tools
   - 2.5 Gate Properties
   - 2.6 Wire Properties
   - 2.7 Wire Name and Bit-Size Labels
   - 2.8 Searching for Gates and Wires
   - 2.9 HTML in Comments
   - 2.10 Printing a Schematic
   - 2.11 Circuit Properties
3. Working with Modules
   - 3.1 Modules Implementations versus Module Instances
   - 3.2 Creating Module Instances
   - 3.3 Module Hierarchy
   - 3.4 Creating and Manipulating Modules
   - 3.5 Editing Module Definitions
   - 3.6 Editing Module Interfaces
4. HDL Modules
   - 4.1 HDL Editor Window
   - 4.2 Verilog Basics
   - 4.3 Data Types
   - 4.4 Expressions
   - 4.5 Compiler Directives
   - 4.6 Module Declarations
   - 4.7 Netlist Modules
   - 4.8 Behavioral Modules
   - 4.9 Module Parameters
   - 4.10 Specify Blocks
5. Using the Simulator with TkGate
   - 5.1 Starting the Simulator
   - 5.2 Observing the Output
   - 5.3 Controlling the Input
   - 5.4 Setting Breakpoints
   - 5.5 Initializing Memories
   - 5.6 Simulation Scripts
   - 5.7 Using the Error Reporter
   - 5.8 Gate Delay Files
6. Gate Microcode and Assembly Compiler (gmac)
   - 6.1 Defining Memory Banks
   - 6.2 Defining the Micro-Instruction Set
   - 6.3 Writing the Micro-Program
   - 6.4 Defining the Macro-Instruction Set
   - 6.5 Writing the Macro-Program
7. Making Virtual Peripheral Devices (VPDs)
   - 7.1 Overview of Virtual Peripheral Device Design
   - 7.2 Installing VPDs
   - 7.3 The Tcl-Side Interface
   - 7.4 The Verilog-Side Interface
8. Setting TkGate Options
   - 8.1 General Options
   - 8.2 Interface Options
   - 8.3 Toolbar Options
   - 8.4 HDL Options
   - 8.5 Print Options
   - 8.6 Simulate Options
   - 8.7 Library Options
   - 8.8 Security Options
   - 8.9 Color Options
   - 8.10 HTML Options
9. TkGate Library Components
   - 9.1 TTYs
   - 9.2 Drink Machine
   - 9.3 Timers and One-Shots
   - 9.4 TTL Devices

##### Appendices

1. List of Built-In Gate Types
2. List of System Tasks
3. List of Simulator Error Messages
4. Using the Verga Simulator in Stand-Alone Mode
5. Sample Gmac Input File